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ISPPAC-POWR1220AT8
In-System Programmable Power Supply Monitoring, Sequencing and Margining Controller
June 2008 Data Sheet DS1015
(R)
Features
Monitor, Control, and Margin Multiple Power Supplies
* Simultaneously monitors up to 12 power supplies * Provides up to 20 output control signals * Provides up to eight analog outputs for margining/trimming power supply voltages * Programmable digital and analog circuitry
Application Block Diagram
Primary Supply 3.3V Primary Supply 2.5V Primary Supply 1.8V Primary Supply
* * * *
Trim and margin up to eight power supplies Dynamic voltage control through I2C Four hardware selectable voltage profiles Independent Digital Closed-Loop Trim function for each output
T r i m / Ma r g i n
Power Supply Margin and Trim Functions
POL#1
Primary Supply
POL#N Other Control/Supervisory Signals 8 Analog Trim Outputs Power Supply Margin/Trim Control Block ADC 4 Timers 6 Digital Inputs I2C Interface 16 Digital Outputs 4 MOSFET Drivers
Embedded PLD for Sequence Control Embedded Programmable Timers
* Four independent timers * 32s to 2 second intervals for timing sequences
12 Analog Inputs and Voltage Monitors
CPLD 48 Macrocells 83 Inputs I2C Bus
Analog Input Monitoring
* 12 independent analog monitor inputs * Differential inputs for remote ground sense * Two programmable threshold comparators per analog input * Hardware window comparison * 10-bit ADC for I2C monitoring
CPU
ISPPAC-POWR1220AT8
Description
Lattice's Power Manager II ISPPAC-POWR1220AT8 is a general-purpose power-supply monitor, sequence and margin controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS(R) technology. The ISPPAC-POWR1220AT8 device provides 12 independent analog input channels to monitor up to 12 power supply test points. Each of these input channels offers a differential input to support remote ground sensing, and has two independently programmable comparators to support both high/low and in-bounds/ out-of-bounds (window-compare) monitor functions. Six general-purpose digital inputs are also provided for miscellaneous control functions. The ISPPAC-POWR1220AT8 provides 20 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Four of these outputs
High-Voltage FET Drivers
* Power supply ramp up/down control * Programmable current and voltage output * Independently configurable for FET control or digital output
2-Wire (I2C/SMBusTM Compatible) Interface
* * * * * Comparator status monitor ADC readout Direct control of inputs and outputs Power sequence control Dynamic trimming/margining control
3.3V Operation, Wide Supply Range 2.8V to 3.96V
* In-system programmable through JTAG * Industrial temperature range: -40C to +85C * 100-pin TQFP package, lead-free option
(c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1015_01.5
Digital Monitoring
* 48-macrocell CPLD implements both state machines and combinatorial logic functions
Enables
Voltage Monitoring
Other Board Circuitry
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The ISPPAC-POWR1220AT8 incorporates a 48-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32s to 2 seconds. The CPLD is programmed using LogiBuilderTM, an easy-to-learn language integrated into the PAC-Designer(R) software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. In addition to the sequence control functions, the ISPPAC-POWR1220AT8 incorporates eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. The trimming voltage can be set to four hardware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I2C bus. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The operating voltage profile can either be selected using external hardware pins or through the PLD outputs. The on-chip 10-bit A/D converter can both be used to monitor the VMON voltage through the I2C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the ISPPAC-POWR1220AT8 device. The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN5, control the output pins, and load the DACs for the generation of the trimming voltage of the external DC-DC converter. Figure 1-1. ISPPAC-POWR1220AT8 Block Diagram
VPS0 VPS1 VMON1+ VMON1GS VMON2+ VMON2GS VMON3+ VMON3GS VMON4+ VMON4GS VMON5+ VMON5GS VMON6+ VMON6GS VMON7+ VMON7GS VMON8+ VMON8GS VMON9+ VMON9GS VMON10+ VMON10GS VMON11+ VMON11GS VMON12+ VMON12GS IN1 IN2 IN3 IN4 IN5 IN6
VOLTAGE OUTPUT DACS (8) DAC DAC DAC DAC DAC DAC DAC DAC
4 FET DRIVERS
TRIM1 TRIM2 TRIM3 TRIM4 TRIM5 TRIM6 TRIM7 TRIM8
ADC
MARGIN/TRIM CONTROL LOGIC
12 ANALOG INPUTS AND VOLTAGE MONITORS 6 DIGITAL INPUTS
VCCPROG VCCINP VCCD (3) VCCA
HVOUT1 HVOUT2 HVOUT3 HVOUT4
OUTPUT ROUTING POOL
CPLD 48 MACROCELLS 83 INPUTS
JTAG LOGIC
CLOCK OSCILLATOR
TIMERS (4)
I 2C INTERFACE
OUT5/SMBA OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20
16 OPEN-DRAIN DIGITAL OUTPUTS
ATDI TDI SELTDI TCK TMS TDO VCCJ
SCL
PLDCLK
MCLK
RESETb
SDA
GNDA (2)
GNDD (6)
1-2
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Pin Descriptions
Number 89 90 97 1 2 4 6 7 47 46 50 48 52 51 54 53 56 55 58 57 62 61 64 63 66 65 68 67 70 69 72 71 Name VPS0 VPS1 IN12 IN23 IN3
3
Pin Type Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input
Voltage Range VCCD VCCD VCCINP1 VCCINP1 VCCINP
1
Description Trim Select Input 0 Registered by MCLK Trim Select Input 1 Registered by MCLK PLD Logic Input 1 Registered by MCLK PLD Logic Input 2 Registered by MCLK PLD Logic Input 3 Registered by MCLK PLD Logic Input 4 Registered by MCLK PLD Logic Input 5 Registered by MCLK PLD Logic Input 6 Registered by MCLK Voltage Monitor 1 Input Voltage Monitor 1 Ground Sense Voltage Monitor 2 Input Voltage Monitor 2 Ground Sense Voltage Monitor 3 Input Voltage Monitor 3 Ground Sense Voltage Monitor 4 Input Voltage Monitor 4 Ground Sense Voltage Monitor 5 Input Voltage Monitor 5 Ground Sense Voltage Monitor 6 Input Voltage Monitor 6 Ground Sense Voltage Monitor 7 Input Voltage Monitor 7 Ground Sense Voltage Monitor 8 Input Voltage Monitor 8 Ground Sense Voltage Monitor 9 Input Voltage Monitor 9 Ground Sense Voltage Monitor 10 Input Voltage Monitor 10 Ground Sense Voltage Monitor 11 Input Voltage Monitor 11 Ground Sense Voltage Monitor 12 Input Voltage Monitor 12 Ground Sense Digital Ground Analog Ground Core VCC, Main Power Supply Analog Power Supply VCC for IN[1:6] Inputs VCC for JTAG Logic Interface Pins VCC for E2 Programming when the Device is Not Powered by VCCD or VCCA Open-Drain Output 1
IN43 IN53 IN6
3
VCCINP1 VCCINP1 VCCINP1 -0.3V to 5.75V4 -0.2V to 0.3V5 -0.3V to 5.75V4 -0.2V to 0.3V5 -0.3V to 5.75V4 -0.2V to 0.3V
5
VMON1 VMON1GS VMON2 VMON2GS VMON3 VMON3GS VMON4 VMON4GS VMON5 VMON5GS VMON6 VMON6GS VMON7 VMON7GS VMON8 VMON8GS VMON9 VMON9GS VMON10 VMON11 VMON12
-0.3V to 5.75V4 -0.2V to 0.3V5 -0.3V to 5.75V -0.2V to 0.3V5 -0.3V to 5.75V -0.2V to 0.3V5 -0.3V to 5.75V -0.2V to 0.3V5 -0.3V to 5.75V4 -0.2V to 0.3V5 -0.3V to 5.75V4 -0.2V to 0.3V5 -0.3V to 5.75V4 -0.2V to 0.3V5 -0.3V to 5.75V -0.2V to 0.3V5 -0.3V to 5.75V -0.2V to 0.3V5 Ground Ground 2.8V to 3.96V 2.8V to 3.96V 2.25V to 3.6V 2.25V to 3.6V 3.0V to 3.6V 0V to 10V
4 4 4 4 4
VMON10GS Analog Input VMON11GS Analog Input VMON12GS Analog Input Ground Ground Power Power Power Power Power Open Drain Output6
3, 22, 36, GNDD8 43, 88, 98 45, 87 60 5 33 39 GNDA8 VCCA VCCJ VCCPROG
7
13, 38, 94 VCCD7 VCCINP
86
HVOUT1
Current Source/Sink
12.5A to 100A Source High-voltage FET Gate Driver 1 100A to 3000A Sink
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Pin Descriptions (Cont.)
Number 85 Name HVOUT2 Pin Type Open Drain Output6 Current Source/Sink Open Drain Output6 42 HVOUT3 Current Source/Sink Open Drain Output6 40 HVOUT4 Current Source/Sink Voltage Range 0V to 10V Description Open-Drain Output 2
12.5A to 100A Source High-voltage FET Gate Driver 2 100A to 3000A Sink 0V to 10V Open-Drain Output 3 12.5A to 100A Source High-voltage FET Gate Driver 3 100A to 3000A Sink 0V to 10V Open-Drain Output 4 12.5A to 100A Source High-voltage FET Gate Driver 4 100A to 3000A Sink 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset Open-Drain Output 5, (SMBUS Alert Active Low) Open-Drain Output 6 Open-Drain Output 7 Open-Drain Output 8 Open-Drain Output 9 Open-Drain Output 10 Open-Drain Output 11 Open-Drain Output 12 Open-Drain Output 13 Open-Drain Output 14 Open-Drain Output 15 Open-Drain Output 16 Open-Drain Output 17 Open-Drain Output 18 Open-Drain Output 19 Open-Drain Output 20 Trim DAC Output 1
8 9 10 11 12 14 15 16 17 18 19 20 21 23 24 25 84
OUT5_SMBA Open Drain Output6 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 TRIM1 Open Drain Output6 Open Drain Output6 Open Drain Output6 Open Drain Output6 Open Drain Output6 Open Drain Output6 Open Drain Output
6
Open Drain Output6 Open Drain Output6 Open Drain Output6 Open Drain Output Open Drain Output Open Drain Output Analog Output
6
Open Drain Output6
6 6 6
Open Drain Output
83
TRIM2
Analog Output
Trim DAC Output 2
82
TRIM3
Analog Output
Trim DAC Output 3
80
TRIM4
Analog Output
Trim DAC Output 4
79
TRIM5
Analog Output
Trim DAC Output 5
75
TRIM6
Analog Output
Trim DAC Output 6
74
TRIM7
Analog Output
Trim DAC Output 7
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Pin Descriptions (Cont.)
Number 73 91 95 96 34 37 28 31 30 32 92 93 44, 59 Name TRIM8 RESETb9 PLDCLK MCLK TDO TCK TMS TDI ATDI TDISEL SCL SDA RESERVED Pin Type Analog Output Digital I/O Digital Output Digital I/O Digital Output Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input Digital I/O Voltage Range -320mV to +320mV from Programmable DAC Offset 0V to 3.96V 0V to 3.96V 0V to 3.96V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V Description Trim DAC Output 8 Device Reset (Active Low) 250kHz PLD Clock Output (Tristate), CMOS Output 8MHz Clock I/O (Tristate), CMOS Drive JTAG Test Data Out JTAG Test Clock Input JTAG Test Mode Select JTAG Test Data In, TDISEL pin = 1 JTAG Test Data In (Alternate), TDISEL Pin = 0 Select TDI/ATDI Input I2C Serial Clock Input I2C Serial Data, Bi-directional Pin Reserved - Do Not Connect No Internal Connection
26, 27, 29, 35, 41, 49, NC 76, 77, 78, 81, 99, 100
1. 2. 3. 4. 5.
6. 7. 8. 9.
[IN1...IN6] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. IN1 pin can also be controlled through JTAG interface. [IN2..IN6] can also be controlled through I2C/SMBus interface. The VMON inputs can be biased independently from VCCA. Unused VMONs should be tied to GNDD. The VMONGS inputs are the ground sense line for each given VMON pin. The VMON input pins along with the VMONGS ground sense pins implement a differential pair for each voltage monitor to allow remote sense at the load. VMONGS lines must be connected and are not to exceed -0.2V - +0.3V in reference to the GNDA pin. Open-drain outputs require an external pull-up resistor to a supply. VCCD and VCCA pins must be connected together on the circuit board. GNDA and GNDD pins must be connected together on the circuit board. The RESETb pin should only be used for cascading two or more ISPPAC-POWR1220AT8 devices.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied.
Symbol VCCD VCCA VCCINP VCCJ VCCPROG VIN VMON+ VMONGS VTRI ISINKMAXTOTAL TS TA Core supply Analog supply Digital input supply (IN[1:6]) JTAG logic supply E programming supply Digital input voltage (all digital I/O pins) VMON input voltage VMON input voltage ground sense Voltage applied to tri-stated pins Maximum sink current on any output Storage temperature Ambient temperature -65 -65 HVOUT[1:4] OUT[5:20]
2
Parameter
Conditions
Min. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max. 4.5 4.5 6 6 4 6 6 6 11 6 23 150 125
Units V V V V V V V V V V mA
o o
C
C
Recommended Operating Conditions
Symbol VCCD, VCCA VCCINP VCCJ VCCPROG VIN VMON VMONGS VOUT TAPROG TA Parameter Core supply voltage at pin Digital input supply for IN[1:6] at pin JTAG logic supply voltage at pin E2 programming supply at pin Input voltage at digital input pins Input voltage at VMON pins Input voltage at VMONGS pins OUT[5:20] pins Open-drain output voltage Ambient temperature during programming Ambient temperature Power applied HVOUT[1:4] pins in opendrain mode During E2 programming Conditions Min. 2.8 2.25 2.25 3.0 -0.3 -0.3 -0.2 -0.3 -0.3 -40 -40 Max. 3.96 5.5 3.6 3.6 5.5 5.9 0.3 5.5 10.4 85 85 Units V V V V V V V V V
o
C C
o
Analog Specifications
Symbol ICC
1
Parameter Supply current Supply current Supply current Supply current
Conditions
Min.
Typ.
Max. 40 5 1
Units mA mA mA mA
ICCINP ICCJ ICCPROG
During programming cycle
40
1. Includes currents on VCCD and VCCA supplies.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Voltage Monitors
Symbol RIN CIN VMON Range VZ Sense VMON Accuracy HYST CMR Parameter Input resistance Input capacitance Programmable trip-point range Near-ground sense threshold Absolute accuracy of any trip-point1 Hysteresis of any trip-point (relative to setting) Common mode rejection 0.075 70 75 0.2 1 60 Conditions Min. 55 Typ. 65 8 5.734 80 0.7 Max. 75 Units k pF V mV % % dB
1. Guaranteed by characterization across VCCA range, operating temperature, process.
High Voltage FET Drivers
Symbol VPP Parameter Gate driver output voltage Conditions 10V setting 8V setting 6V setting Gate driver source current (HIGH state) Four settings in software FAST OFF mode IOUTSINK Gate driver sink current (LOW state) Controlled ramp settings 2000 Min. 9.6 7.7 5.8 Typ. 10 8 6 12.5 IOUTSRC 25 50 100 3000 100 250 500 A A Max. 10.4 8.3 6.2 V Units
1-7
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Margin/Trim DAC Output Characteristics
Symbol Resolution FSR LSB IOUT Full scale range LSB step size Output source/sink current Offset 1 BPZ Bipolar zero output voltage (code=80h) Offset 2 Offset 3 Offset 4 DAC code changed from 80H to FFH or 80H to 00H Single DAC code change MCLK = 8MHz Full scale DAC corresponds to 5% supply voltage variation -1% 256 50
2
Parameter
Conditions
Min
Typ 8(7+sign) +/-320 2.5
Max
Units bits mV mV
-200 0.6 0.8 1.0 1.25
200
A
V
TS
TrimCell output voltage settling time1
2.5
ms s pF s
C_LOAD TUPDATEM TOSE
Maximum load capacitance Update time through I C port
2
260 +1%
Total open loop supply voltage error3
V/V
1. To 1% of set value with 50pf load connected to trim pins. 2. Total time required to update a single TRIMx output value by setting the associated DAC through the I 2C port. 3. This is the total resultant error in the trimmed power supply output voltage referred to any DAC code due to the DAC's INL, DNL, gain, output impedance, offset error and bipolar offset error across the industrial temperature range and the ispPAC-POWR1200AT8 operating V CCA and VCCD ranges.
ADC Characteristics
Symbol TCONVERT VIN Parameter ADC Resolution Conversion Time Input range Full Scale Time from I C Request Programmable Attenuator = 1 Programmable Attenuator = 3 Programmable Attenuator = 1 Programmable Attenuator = 3 Programmable Attenuator = 3 0 0 2 6 +/- 0.1
2
Conditions
Min.
Typ. 10
Max. 200 2.048 5.9
1
Units Bits s V V mV mV %
ADC Step Size LSB Eattenuator Error Due to Attenuator
1. Maximum voltage is limited by VMONX pin (theoretical maximum is 6.144V).
ADC Error Budget Across Entire Operating Temperature Range
Symbol Parameter Conditions Measurement Range 600 mV - 2.048V, VMONxGS > -100mV, Attenuator =1 TADC Error Total Measurement Error at Any Voltage1 Measurement Range 600 mV - 2.048V, VMONxGS > -200mV, Attenuator =1 Measurement Range 0 - 2.048V, VMONxGS > -200mV, Attenuator =1
1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
Min. -8
Typ. +/-4 +/-6 +/-10
Max. 8
Units mV mV mV
1-8
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Power-On Reset
Symbol TRST TSTART TGOOD TBRO TPOR VTL VTH VT CL Parameter Delay from VTH to start-up state Delay from RESETb HIGH to PLDCLK rising edge Power-on reset to valid VMON comparator output and AGOOD is true Minimum duration brown out required to trigger RESETb Delay from brown out to reset state. Threshold below which RESETb is LOW1 Threshold above which RESETb is HIGH Threshold above which RESETb is valid1 Capacitive load on RESETb for master/slave operation
1
Conditions
Min.
Typ.
Max. 100
Units s s ms
5 2.5 1
10
5 13 2.3
s s V V V
2.7 0.8 200
pF
1. Corresponds to VCCA and VCCD supply voltages.
Figure 1-2. ispPAC-POWR1220ATE Power-On Reset
VTH VTL VT TBRO VCC
TRST Start Up State Reset State
TPOR
RESETb
MCLK
PLDCLK
TSTART Analog Calibration TGOOD AGOOD (Internal)
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
AC/Transient Characteristics
Over Recommended Operating Conditions
Symbol Voltage Monitors tPD16 tPD64 Oscillators fCLK fCLKEXT fPLDCLK Timers Timeout Range Resolution Accuracy Range of programmable timers (128 steps) Spacing between available adjacent timer intervals Timer accuracy fCLK = 8MHz -6.67 fCLK = 8MHz 0.032 1966 13 -12.5 ms % % Internal master clock frequency (MCLK) Externally applied master clock (MCLK) PLDCLK output frequency fCLK = 8MHz 7.6 7.2 250 8 8.4 8.8 MHz MHz kHz Propagation delay input to output glitch filter OFF Propagation delay input to output glitch filter ON 16 64 s s Parameter Conditions Min. Typ. Max. Units
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Digital Specifications
Over Recommended Operating Conditions
Symbol IIL,IIH IOH-HVOUT IPU Parameter Input leakage, no pull-up/pull-down Output leakage current Input pull-up current (TMS, TDI, TDISEL, ATDI, MCLK) VPS[0:1], TDI, TMS, ATDI, TDISEL, 3.3V supply VIL Voltage input, logic low1 VPS[0:1], TDI, TMS, ATDI, TDISEL, 2.5V supply SCL, SDA IN[1:6] VPS[0:1], TDI, TMS, ATDI, TDISEL, 3.3V supply VIH Voltage input, logic high1 VPS[0:1], TDI, TMS, ATDI, TDISEL, 2.5V supply SCL, SDA IN[1:6] HVOUT[1:4] (open drain mode), VOL VOH ISINKTOTAL OUT[5:20] TDO,MCLK,PLDCLK TDO, MCLK, PLDCLK All digital outputs ISINK = 10mA ISINK = 20mA ISINK = 4mA ISRC = 4mA 2.0 HVOUT[1:4] in open drain mode and pulled up to 10V 35 70 0.8 Conditions Min. Typ. Max. +/-10 60 Units A A A
0.7 30% VCCD 30% VCCINP
V
1.7 70% VCCD 70% VCCINP VCCD VCCINP 0.8 0.8 0.4 VCCD - 0.4 130
V
V V mA
1. VPS[0:1], SCL, SDA referenced to VCCD; IN[1:6] referenced to VCCINP; TDO, TDI, TMS, ATDI, TDISEL referenced to VCCJ.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
I2C Port Characteristics
100KHz Symbol FI2C TSU;STA THD;STA TSU;DAT TSU;STO THD;DAT TLOW THIGH TF TR TTIMEOUT TPOR TBUF I C clock/data rate After start After start Data setup Stop setup Data hold; SCL= Vih_min = 2.1V Clock low period Clock high period Fall time; 2.25V to 0.65V Rise time; 0.65V to 2.25V Detect clock low timeout Device must be operational after power-on reset Bus free time between stop and start condition 25 500 4.7 4.7 4 250 4 0.3 4.7 4 300 1000 35 25 500 1.3 3.45
2
400KHz Min. 0.6 0.6 100 0.6 0.3 1.3 0.6 300 300 35 0.9 Max. 400
1
Definition
Min.
Max. 100
1
Units KHz us us ns us us us us ns ns ms ms us
1. If FI2C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this case, waiting for the TCONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for readout. When FI2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Timing for JTAG Operations
Symbol tISPEN tISPDIS tHVDIS tHVDIS tCEN tCDIS tSU1 tH tCKH tCKL fMAX tCO tPWV tPWP Parameter Program enable delay time Program disable delay time High voltage discharge time, program High voltage discharge time, erase Falling edge of TCK to TDO active Falling edge of TCK to TDO disable Setup time Hold time TCK clock pulse width, high TCK clock pulse width, low Maximum TCK clock frequency Falling edge of TCK to valid output Verify pulse width Programming pulse width Conditions Min. 10 30 30 200 -- -- 5 10 20 20 -- -- 30 20 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- 15 15 -- -- -- -- 25 15 -- -- Units s s s s ns ns ns ns ns ns MHz ns s ms
Figure 1-3. Erase (User Erase or Erase All) Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tGKL
tH
tSU1
Clock to Shift-IR state and shift in the Discharge Instruction, then clock to the Run-Test/Idle state
tH tCKH
tSU1
tH tCKH
tSU1 tGKL
tH tCKH
tSU1
tH tCKH
TCK
VIL
tSU2
Specified by the Data Sheet
State
Update-IR
Run-Test/Idle (Erase)
Select-DR Scan
Run-Test/Idle (Discharge)
Figure 1-4. Programming Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWP
tSU1
tH tCKH
Clock to Shift-IR state and shift in the next Instruction, which will stop the discharge process
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
TCK
VIL
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Update-IR
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Lattice Semiconductor
Figure 1-5. Verify Timing Diagram
VIH
ISPPAC-POWR1220AT8 Data Sheet
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWV
tSU1
tH tCKH
Clock to Shift-IR state and shift in the next Instruction
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
TCK
VIL
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Update-IR
Figure 1-6. Discharge Timing Diagram
VIH
tHVDIS (Actual)
Clock to Shift-IR state and shift in the Verify Instruction, then clock to the Run-Test/Idle state
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWP
tSU1
tH tCKH
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
tSU1 tPWV
Actual
tH tCKH
TCK
VIL
tPWV
Specified by the Data Sheet
State
Update-IR
Run-Test/Idle (Erase or Program)
Select-DR Scan
Run-Test/Idle (Verify)
Theory of Operation
Analog Monitor Inputs
The ISPPAC-POWR1220AT8 provides 12 independently programmable voltage monitor input circuits as shown in Figure 1-7. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 368 programmable trip points over the range of 0.664V to 5.734V. Additionally, a 75mV `zero-detect' threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to ground level. This feature is especially useful for determining if a power supply's output has decayed to a substantially inactive condition after it has been switched off.
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Lattice Semiconductor
Figure 1-7. ISPPAC-POWR1220AT8 Voltage Monitors
ISPPAC-POWR1220AT8
ISPPAC-POWR1220AT8 Data Sheet
To ADC
Differential Input Buffer x VMONx + VMONxGS Trip Point A
Comp A
Comp A/Window Select VMONxA Logic Signal
MUX
-
Glitch Filter
PLD Array Comp B + Trip Point B - Glitch Filter VMONxB Logic Signal
Analog Input
Window Control
Filtering VMONx Status I2C Interface Unit
Figure 1-7 shows the functional block diagram of one of the 12 voltage monitor inputs - `x' (where x = 1...12). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section provides a differential input buffer to monitor the power supply voltage through VMONx+ (to sense the positive terminal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the ISPPAC-POWR1220AT8 device ground and the ground potential at the sensed node on the circuit board. The voltage output of the differential input buffer is monitored by two individually programmable trip-point comparators, shown as CompA and CompB. Table 1-1 shows all 368 trip points spanning the range 0.664V to 5.734V to which a comparator's threshold can be set. Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its programmed trip point setting, otherwise it outputs a LOW signal. A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 1-3 lists the typical hysteresis versus voltage monitor trip-point.
AGOOD Logic Signal
All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital glitch filters are also initialized. This process completion is signalled by an internally generated logic signal: AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 1-8 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Figure 1-8. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output, (b) Corresponding to Upper and Lower Trip Points
Monitored Power Supply Votlage
UTP LTP
(a)
(b) Comparator Logic Output
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
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Lattice Semiconductor
Table 1-1. Trip Point Table Used For Over-Voltage Detection
Fine Range Setting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Low-V Sense
ISPPAC-POWR1220AT8 Data Sheet
Coarse Range Setting 1 0.790 0.786 0.782 0.778 0.773 0.769 0.765 0.761 0.756 0.752 0.748 0.744 0.739 0.735 0.731 0.727 0.723 0.718 0.714 0.710 0.706 0.701 0.697 0.693 0.689 0.684 0.680 0.676 0.672 0.668 2 0.941 0.936 0.930 0.926 0.921 0.916 0.911 0.906 0.901 0.896 0.891 0.886 0.881 0.876 0.871 0.866 0.861 0.856 0.851 0.846 0.841 0.836 0.831 0.826 0.821 0.816 0.810 0.805 0.800 0.795 3 1.120 1.114 1.108 1.102 1.096 1.090 1.084 1.078 1.072 1.066 1.060 1.054 1.048 1.042 1.036 1.030 1.024 1.018 1.012 1.006 1.000 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952 0.946 4 1.333 1.326 1.319 1.312 1.305 1.298 1.290 1.283 1.276 1.269 1.262 1.255 1.248 1.240 1.233 1.226 1.219 1.212 1.205 1.198 1.190 1.183 1.176 1.169 1.162 1.155 1.148 1.140 1.133 1.126 5 1.580 1.571 1.563 1.554 1.546 1.537 1.529 1.520 1.512 1.503 1.495 1.486 1.478 1.470 1.461 1.453 1.444 1.436 1.427 1.419 1.410 1.402 1.393 1.385 1.376 1.369 1.361 1.352 1.344 -- 6 1.885 1.874 1.864 1.854 1.844 1.834 1.825 1.815 1.805 1.795 1.785 1.774 1.764 1.754 1.744 1.734 1.724 1.714 1.704 1.694 1.684 1.673 1.663 1.653 1.643 1.633 1.623 1.613 1.603 1.593 7 2.244 2.232 2.220 2.209 2.197 2.185 2.173 2.161 2.149 2.137 2.125 2.113 2.101 2.089 2.077 2.064 2.052 2.040 2.028 2.016 2.004 1.992 1.980 1.968 1.956 1.944 1.932 1.920 1.908 1.896 8 2.665 2.650 2.636 2.622 2.607 2.593 2.579 2.565 2.550 2.536 2.522 2.507 2.493 2.479 2.465 2.450 2.436 2.422 2.407 2.393 2.379 2.365 2.350 2.337 2.323 2.309 2.294 2.280 2.266 2.251 9 3.156 3.139 3.123 3.106 3.089 3.072 3.056 3.039 3.022 3.005 2.988 2.971 2.954 2.937 2.920 2.903 2.886 2.869 2.852 2.836 2.819 2.802 2.785 2.768 2.752 2.735 2.718 2.701 2.684 -- 10 3.758 3.738 3.718 3.698 3.678 3.657 3.637 3.618 3.598 3.578 3.558 3.537 3.517 3.497 3.477 3.457 3.437 3.416 3.396 3.376 3.356 3.336 3.316 3.296 3.276 3.256 3.236 3.216 3.196 3.176 11 4.818 4.792 4.766 4.741 4.715 4.689 4.663 4.638 4.612 4.586 4.561 4.535 4.509 4.483 4.457 4.431 4.406 4.380 4.355 4.329 4.303 4.277 4.251 4.225 4.199 4.174 4.149 4.123 4.097 4.071 12 5.734 5.703 5.674 5.643 5.612 5.581 5.550 5.520 5.489 5.459 5.428 5.397 5.366 5.336 5.305 5.274 5.244 5.213 5.183 5.152 5.121 5.090 5.059 5.030 4.999 4.968 4.937 4.906 4.876 4.845
75mV
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Lattice Semiconductor
Table 1-2. Trip Point Table Used For Under-Voltage Detection
Fine Range Setting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Low-V Sense
ISPPAC-POWR1220AT8 Data Sheet
Coarse Range Setting 1 0.786 0.782 0.778 0.773 0.769 0.765 0.761 0.756 0.752 0.748 0.744 0.739 0.735 0.731 0.727 0.723 0.718 0.714 0.710 0.706 0.701 0.697 0.693 0.689 0.684 0.680 0.676 0.672 0.668 0.664 2 0.936 0.930 0.926 0.921 0.916 0.911 0.906 0.901 0.896 0.891 0.886 0.881 0.876 0.871 0.866 0.861 0.856 0.851 0.846 0.841 0.836 0.831 0.826 0.821 0.816 0.810 0.805 0.800 0.795 0.790 3 1.114 1.108 1.102 1.096 1.090 1.084 1.078 1.072 1.066 1.060 1.054 1.048 1.042 1.036 1.030 1.024 1.018 1.012 1.006 1.000 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952 0.946 0.940 4 1.326 1.319 1.312 1.305 1.298 1.290 1.283 1.276 1.269 1.262 1.255 1.248 1.240 1.233 1.226 1.219 1.212 1.205 1.198 1.190 1.183 1.176 1.169 1.162 1.155 1.148 1.140 1.133 1.126 1.119 5 1.571 1.563 1.554 1.546 1.537 1.529 1.520 1.512 1.503 1.495 1.486 1.478 1.470 1.461 1.453 1.444 1.436 1.427 1.419 1.410 1.402 1.393 1.385 1.376 1.369 1.361 1.352 1.344 1.335 -- 6 1.874 1.864 1.854 1.844 1.834 1.825 1.815 1.805 1.795 1.785 1.774 1.764 1.754 1.744 1.734 1.724 1.714 1.704 1.694 1.684 1.673 1.663 1.653 1.643 1.633 1.623 1.613 1.603 1.593 1.583 7 2.232 2.220 2.209 2.197 2.185 2.173 2.161 2.149 2.137 2.125 2.113 2.101 2.089 2.077 2.064 2.052 2.040 2.028 2.016 2.004 1.992 1.980 1.968 1.956 1.944 1.932 1.920 1.908 1.896 1.884 8 2.650 2.636 2.622 2.607 2.593 2.579 2.565 2.550 2.536 2.522 2.507 2.493 2.479 2.465 2.450 2.436 2.422 2.407 2.393 2.379 2.365 2.350 2.337 2.323 2.309 2.294 2.280 2.266 2.251 2.236 9 3.139 3.123 3.106 3.089 3.072 3.056 3.039 3.022 3.005 2.988 2.971 2.954 2.937 2.920 2.903 2.886 2.869 2.852 2.836 2.819 2.802 2.785 2.768 2.752 2.735 2.718 2.701 2.684 2.667 -- 10 3.738 3.718 3.698 3.678 3.657 3.637 3.618 3.598 3.578 3.558 3.537 3.517 3.497 3.477 3.457 3.437 3.416 3.396 3.376 3.356 3.336 3.316 3.296 3.276 3.256 3.236 3.216 3.196 3.176 3.156 11 4.792 4.766 4.741 4.715 4.689 4.663 4.638 4.612 4.586 4.561 4.535 4.509 4.483 4.457 4.431 4.406 4.380 4.355 4.329 4.303 4.277 4.251 4.225 4.199 4.174 4.149 4.123 4.097 4.071 4.045 12 5.703 5.674 5.643 5.612 5.581 5.550 5.520 5.489 5.459 5.428 5.397 5.366 5.336 5.305 5.274 5.244 5.213 5.183 5.152 5.121 5.090 5.059 5.030 4.999 4.968 4.937 4.906 4.876 4.845 4.815
75mV
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Table 1-3. Comparator Hysteresis vs. Trip-Point
Trip-point Range (V) Low Limit 0.664 0.79 0.94 1.119 1.326 1.583 1.884 2.236 2.65 3.156 4.045 4.815 75 mV High Limit 0.79 0.941 1.12 1.333 1.58 1.885 2.244 2.665 3.156 3.758 4.818 5.734
ISPPAC-POWR1220AT8 Data Sheet
Hysteresis (mV) 8 10 12 14 17 20 24 28 34 40 51 61 0 (Disabled)
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA "ANDed" with COMPB signal) and a multiplexer that supports the ability to develop a `window' function without using any of the PLD's resources. Through the use of the multiplexer, voltage monitor's `A' output may be set to report either the status of the `A' comparator, or the window function of both comparator outputs. The voltage monitor's `A' output indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases where the threshold of the `A' comparator is set to a value higher than that of the `B' comparator. Table 1-4 shows the operation of window function logic. Table 1-4. Voltage Monitor Windowing Logic
Input Voltage VIN < Trip-point B < Trip-point A Trip-point B < VIN < Trip-point A Trip-point B < Trip-point A < VIN Comp A 0 0 1 Comp B 0 1 1 Window (B and Not A) 0 1 0 Comment Outside window, low Inside window Outside window, high
Note that when the `A' output of the voltage monitor circuit is set to windowing mode, the `B' output continues to monitor the output of the `B' comparator. This can be useful in that the `B' output can be used to augment the windowing function by determining if the input is above or below the windowing range. The third section in the ISPPAC-POWR1220AT8's input voltage monitor is a digital filter. When enabled, the comparator output will be delayed by a filter time constant of 64 S, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16S. In both cases, enabled or disabled, the filters also provide synchronization of the input signals to the PLD clock. This synchronous sampling feature effectively eliminates the possibility of race conditions from occurring in any subsequent logic that is implemented in the ISPPAC-POWR1220AT8's internal PLD logic. The comparator status can be read from the I2C interface. For details on the I2C interface, please refer to the I2C/ SMBUS Interface section of this data sheet.
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ISPPAC-POWR1220AT8 Data Sheet
VMON Voltage Measurement with the On-chip Analog to Digital Converter (ADC)
The ispPAC-POWR1220 has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. The ADC is also used in closed loop trimming of DC-DC converters. Close loop trimming is covered later in this document. Figure 1-9. ADC Monitoring VMON1 to VMON12
VMON1
VMON2 Programmable Analog Attenuator Programmable Digital Multiplier
VMON3
To Closed Loop Trim Circuit
ADC MUX
3
1
ADC
10
3
1 12
VMON12 Internal VREF2.048V
To I 2 C Readout Register
VDDA
VDDINP
4 5 1
Internal Control Signal
5 5
From Closed Loop Trim Circuit
From I 2 C ADC MUX Register
Figure 1-9 shows the ADC circuit arrangement within the ISPPAC-POWR1220AT8 device. The ADC can measure all analog input voltages through the multiplexer, ADC MUX. The programmable attenuator between the ADC mux and the ADC can be configured as divided-by-3 or divided-by-1 (no attenuation). The divided-by-3 setting is used to measure voltages from 0V to 6V range and divided-by-1 setting is used to measure the voltages from 0V to 2V range. A microcontroller can place a request for any VMON voltage measurement at any time through the I2C bus. Upon the receipt of an I2C command, the ADC will be connected to the I2C selected VMON through the ADC MUX. The ADC output is then latched into the I2C readout registers. Calculation The algorithm to convert the ADC code to the corresponding voltage takes into consideration the attenuation bit value. In other words, if the attenuation bit is set, then the 10-bit ADC result is automatically multiplied by 3 to calculate the actual voltage at that VMON input. Thus, the I2C readout register is 12 bits instead of 10 bits. The following formula can always be used to calculate the actual voltage from the ADC code. Voltage at the VMONx Pins VMON = ADC code (12 bits1, converted to decimal) * 2mV
1
Note: ADC_VALUE_HIGH (8 bits), ADC_VALUE_LOW (4 bits) read from I2C/SMBUS interface
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Lattice Semiconductor PLD Block
ISPPAC-POWR1220AT8 Data Sheet
Figure 1-10 shows the ISPPAC-POWR1220AT8 PLD architecture, which is derived from the Lattice's ispMACHTM 4000 CPLD. The PLD architecture allows the flexibility in designing various state machines and control functions used for power supply management. The AND array has 83 inputs and generates 243 product terms. These 243 product terms are divided into three groups of 81 for each of the generic logic blocks, GLB1, GLB2, and GLB3. Each GLB is made up of 16 macrocells. In total, there are 48 macrocells in the ISPPAC-POWR1220AT8 device. The output signals of the ISPPAC-POWR1220AT8 device are derived from GLBs as shown in Figure 1-10. Additionally, the GLB3 generates the timer control and trimming block controls. Figure 1-10. ISPPAC-POWR1220AT8 PLD Architecture
Global Reset (Resetb pin)
AGOOD MCLK
81
GLB1 Generic Logic Block 16 Macrocell 81 PT
HVOUT[1..4], OUT[5..8]
IN[1:6]
6
Input Register AND Array 83 Inputs 243 PT GLB2 Generic Logic Block 16 Macrocell 81 PT
VMON[1-12]
24
OUT[9..16]
Input Register
81
4
Output Feedback
81
GLB3 Generic Logic Block 16 Macrocell 81 PT
OUT[17..20] PLD_CLT_EN, PLD_VPS[0:1]
48
Timer0 Timer1 Timer2 Timer3
IRP
14
Timer Clock
PLD Clock
Macrocell Architecture The macrocell shown in Figure 1-11 is the heart of the PLD. The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity control and XOR gates provide additional flexibility for logic synthesis. The flip-flop's clock is driven from the common PLD clock that is generated by dividing the 8 MHz master clock (MCLK) by 32. The macrocell also supports asynchronous reset and preset functions, derived from either product terms, the global reset input, or the power-on reset signal. The resources within the macrocells share routing and contain a product term allocation array. The product term allocation array greatly expands the PLD's ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. All the digital inputs are registered by MCLK and the VMON comparator outputs are registered by the PLD Clock to synchronize them to the PLD logic.
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Figure 1-11. ISPPAC-POWR1220AT8 Macrocell Block Diagram
Global Reset Global Polarity Fuse for Init Product Term Block Init Product Term
ISPPAC-POWR1220AT8 Data Sheet
Power On Reset
Product Term Allocation
PT4 PT3 PT2 PT1 PT0
R D/T
P Q
To ORP
Polarity
CLK Clock Macrocell flip-flop provides D, T, or combinatorial output with polarity
Clock and Timer Functions
Figure 1-12 shows a block diagram of the ISPPAC-POWR1220AT8's internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 1-12. Clock and Timer System
PLD Clock
Timer 0
Internal Oscillator 8MHz
SW0 32
Timer 1 To/From PLD Timer 2
SW1 Timer 3 SW2
MCLK
PLDCLK
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir-
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
cuits, ADC and trim circuits. The ISPPAC-POWR1220AT8 can be programmed to operate in three modes: Master mode, Standalone mode and Slave mode. Table 1-5 summarizes the operating modes of ISPPAC-POWR1220AT8. Table 1-5. ISPPAC-POWR1220AT8 Operating Modes
Timer Operating Mode Standalone Master SW0 Closed Closed SW1 Open Closed Condition When only one ISPPAC-POWR1220AT8 is used. Comments MCLK pin tristated
When more than one ISPPAC-POWR1220AT8 is used in a board, one of them should be configured MCLK pin outputs 8MHz clock to operate in this mode. When more than one ISPPAC-POWR1220AT8s is used in a board. Other than the master, the rest of MCLK pin is input the ISPPAC-POWR1220AT8s should be programmed as slaves.
Slave
Open
Closed
A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing SW2. Each of the four timers provides independent timeout intervals ranging from 32s to 1.96 seconds in 128 steps.
Digital Outputs
The ISPPAC-POWR1220AT8 provides 20 digital outputs, HVOUT[1:4] and OUT[5:20]. Outputs OUT[5:20] are permanently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, LEDs, opto-couplers, and power supply control inputs. The HVOUT[1:4] pins can be configured as either high voltage FET drivers or open drain outputs. Each of these outputs may be controlled either from the PLD or from the I2C bus. The determination whether a given output is under PLD or I2C control may be made on a pin-by-pin basis (see Figure 113). For further details on controlling the outputs through I2C, please see the I2C/SMBUS Interface section of this data sheet. Figure 1-13. Digital Output Pin Configuration
Digital Control from PLD OUTx Pin
Digital Control from I2C Register
High-Voltage Outputs
In addition to being usable as digital open-drain outputs, the ISPPAC-POWR1220AT8's HVOUT1-HVOUT4 output pins can be programmed to operate as high-voltage FET drivers. Figure 1-14 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the PLD or from the I2C bus (see Figure 1-14). For further details on controlling the outputs through I2C, please see the I2C/SMBUS Interface section of this data sheet.
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ISPPAC-POWR1220AT8 Data Sheet
Figure 1-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Charge Pump (6 to 10V) ISOURCE (12.5 to 100 A) Input Supply
+ -
HVOUTx Pin
Digital Control from PLD
ISINK (100 to 500 A) +Fast Turn-off (3000A)
Load
Digital Control from I2C Register
Figure 1-14 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also programmable between 6V and 10V. The maximum voltage levels that are required depend on the gate-to-source threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET's source, since the source pin of the FET to provide a wide range of ramp rates is tied to the supply of the target board. When the HVOUT pin is sourcing current, charging a FET gate, the source current is programmable between 12.5A and 100A. When the driver is turned to the off state, the driver will sink current to ground, and this sink current is also programmable between 3000A and 100A to control the turn-off rate. Programmable Output Voltage Levels for HVOUT1- HVOUT4 There are three selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage that the pin is capable of driving to can be programmed from 6V to 10V in 2V steps.
Controlling Power Supply Output Voltage by Margin/ Trim Block
One of the key features of the ISPPAC-POWR1220AT8 is its ability to make adjustments to the power supplies that it may also be monitoring and/or sequencing. This is accomplished through the Trim and Margin Block of the device. The Trim and Margin Block can adjust voltages of up to eight different power supplies through TrimCells as shown in Figure 1-15. The DC-DC blocks in the figure represent virtually any type of DC power supply that has a trim or voltage adjustment input. This can be an off-the-shelf unit or custom circuit designed around a switching regulator IC. The interface between the ISPPAC-POWR1220AT8 and the DC power supply is represented by a single resistor (R1 to R8) to simplify the diagram. Each of these resistors represents a resistor network. Other control signals driving the Margin/Trim Block are: * VPS [1:0] - Control signals from device pins common to all eight TrimCells, which are used to select the active voltage profile for all TrimCells together. * PLD_VPS[1:0] - Voltage profile selection signals generated by the PLD. These signals can be used instead of the VPS signals from the pins. * ADC input - Used to determine the trimmed DC-DC converter voltage. * PLD_CLT_EN - Only from PLD, used to enable closed loop trimming of all TrimCells together. Next to each DC-DC converter, four voltages are shown. These voltages correspond to the operating voltage profile of the Margin/Trim Block.
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ISPPAC-POWR1220AT8 Data Sheet
When the VPS[1:0] = 00, representing Voltage Profile 0: (Voltage Profile 0 is recommended to be used for the normal circuit operation) The output voltage of the DC-DC converter controlled by the Trim 1 pin of the ISPPAC-POWR1220AT8 will be 1V and that TrimCell is operating in closed loop trim mode. At the same time, the DC-DC converters controlled by Trim 2, Trim 3 and Trim 8 pins output 1.2V, 1.5V and 3.3V respectively. When the VPS[1:0] = 01, representing Voltage Profile 1 being active: The DC-DC output voltage controlled by Trim 1, 2, 3, and 8 pins will be 1.05V, 1.26V, 1.57V, and 3.46V. These supply voltages correspond to 5% above their respective normal operating voltage (also called as margin high). Similarly, when VPS[1:0] = 11, all DC-DC converters are margined low by 5%. Figure 1-15. ISPPAC-POWR1220AT8 Trim and Margin Block
ISPPAC-POWR1220AT8 Margin/Trim Block
VIN
DC-DC
Trim-in
DC-DC Output Voltage Controlled by Profiles 0 1 1V (CLT) 1.05V 2 0.97V 3 0.95V
TrimCell #1
(Closed Loop)
Trim 1
R1*
VIN
1.2V (I2C) 1.26V 1.16V 1.14V
Digital Closed Loop and I2C Interface Control
TrimCell #2
(I2C Update)
Trim 2
R2*
DC-DC
Trim-in
VIN
1.5V (I2C) 1.57V 1.45V 1.42V
VPS[0:1]
TrimCell #3
(I2C Update)
Trim 3
R3*
DC-DC
Trim-in
VIN
3.3V (EE) 3.46V 3.20V 3.13V
TrimCell #8
(Register 0)
Trim 8
R8*
DC-DC
Trim-in
*Indicates resistor network
Input From ADC Mux Read - 10-bit ADC Code
PLD Control Signals PLD_CLT_EN, PLD_VPS[0:1]
There are eight TrimCells in the ISPPAC-POWR1220AT8 device, enabling simultaneous control of up to eight individual power supplies. Each TrimCell can generate up to four trimming voltages to control the output voltage of the DC-DC converter.
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Figure 1-16. TrimCell Driving a Typical DC-DC Converter
ISPPAC-POWR1220AT8 Data Sheet
VOUT
VIN VOUT R3 TrimCell #N DAC R1 R2 Trim DC-DC Converter
Figure 1-16 shows the resistor network between the TrimCell #N in the ISPPAC-POWR1220AT8 and the DC-DC converter. The values of these resistors depend on the type of DC-DC converter used and its operating voltage range. The method to calculate the values of the resistors R1, R2, and R3 are described in a separate application note. Voltage Profile Control The Margin / Trim Block of ISPPAC-POWR1220AT8 consists of eight TrimCells. Because all eight TrimCells in the Margin / Trim Block are controlled by two common voltage profile control signals, they all operate at the same voltage profile. These common voltage profile control signals are derived from a Control Multiplexer. One set of voltage profile control inputs to the control multiplexer is from a pair of device pins: VPS0, VPS1. The second set of voltage profile control inputs is from the PLD: PLD_VPS0, PLD_VPS1. The selection between the two sets of voltage profile control signals is programmable and is stored in the E2CMOS memory.
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Figure 1-17. Voltage Profile Control
ISPPAC-POWR1220AT8 Data Sheet
ISPPAC-POWR1220AT8 Margin/Trim Block
Common Voltage Profile Control Signals
TrimCell #1
Trim 1
TrimCell #2
Trim 2
INT/EXT SELECT (E2CMOS)
TrimCell #3
Trim 3
VPS0 VPS1 PLD Control Signals PLD_VPS[0:1]
2
TrimCell #4
Trim 4
CTRL MUX
2
2
Common Voltage Profile Control Signals
TrimCell #5
Trim 5
TrimCell #6
Trim 6
TrimCell #7
Trim 7
TrimCell #8
Trim 8
TrimCell Architecture The TrimCell block diagram is shown in Figure 1-18. The 8-bit DAC at the output provides the trimming voltage required to set the output voltage of a programmable supply. Each TrimCell can be operated in any one of the four voltage profiles. In each voltage profile the output trimming voltage can be set to a preset value. There are six 8-bit registers in each TrimCell that, depending on the operational mode, set the DAC value. Of these, four DAC values (DAC Register 0 to DAC Register 3) are stored in the E2CMOS memory while the remaining register contents are stored in volatile registers. Two multiplexers (Mode Mux and Profile Mux) control the routing of the code to the DAC. The Profile Mux can be controlled by common TrimCell voltage profile control signals.
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Lattice Semiconductor
Figure 1-18. ISPPAC-POWR1220AT8 Output TrimCell
TRIMCELL ARCHITECTURE
VOLTAGE PROFILE 3 VOLTAGE PROFILE 2 VOLTAGE PROFILE 1 DAC REGISTER 3 (E2CMOS) DAC REGISTER 2 (E2CMOS) DAC REGISTER 1 (E2CMOS) DAC REGISTER 0 (E2CMOS) VOLTAGE PROFILE 0 DAC REGISTER (I2C) CLOSED LOOP TRIM REGISTER 8 VOLTAGE PROFILE 0 MODE SELECT (E2CMOS) 8 8
ISPPAC-POWR1220AT8 Data Sheet
8
11
PROFILE MUX
8
10 01 00
8
DAC
TRIMx
8 2
8
MODE MUX
COMMON TrimCell VOLTAGE PROFILE CONTROL
FROM CLOSED LOOP TRIM CIRCUIT
Figure 1-15 shows four power supply voltages next to each DC-DC converter. When the Profile MUX is set to Voltage Profile 3, the DC supply controlled by Trim 1 will be at 0.95V, the DC supply controlled by Trim 2 will be at 1.14V, 1.43V for Trim 3 and 3.14V for Trim 8. When Voltage Profile 0 is selected, Trim 1 will set the supply to 1V, Trim 2 and Trim 3 will be set by the values that have been loaded using I2C at 1.2 and 1.5V, and Trim 8 will be set to 3.3V. The following table summarizes the voltage profile selection and the corresponding DAC output trimming voltage. The voltage profile selection is common to all eight TrimCells. Table 1-6. TrimCell Voltage Profile and Operating Modes
PLD_VPS[1:0] or VPS[1:0] 11 10 01 00 Selected Voltage Profile Voltage Profile 3 Voltage Profile 2 Voltage Profile 1 Voltage Profile 0 Selected Mode -- -- -- DAC Register 0 Select DAC Register I C Select Digital Closed Loop Trim
2
Trimming Voltage is Controlled by DAC Register 3 (E2CMOS) DAC Register 2 (E2CMOS) DAC Register 1 (E2CMOS) DAC Register 0 (E2CMOS) DAC Register (I2C) Closed Loop Trim Register
TrimCell Operation in Voltage Profiles 1, 2 and 3: The output trimming voltage is determined by the code stored in the DAC Registers 1, 2, and 3 corresponding to the selected Voltage Profile. TrimCell Operation in Voltage Profile 0: The Voltage Profile 0 has three operating modes. They are DAC Register 0 Select mode, DAC Register I2C Select mode and Closed Loop Trim mode. The mode selection is stored in the E2CMOS configuration memory. Each of the eight TrimCells can be independently set to different operating modes during Voltage Profile 0 mode of operation. DAC Register 0 Select Mode: The contents of DAC register 0 are stored in the on-chip E2CMOS memory. When Voltage Profile 0 is selected, the DAC will be loaded with the value stored in DAC Register 0.
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ISPPAC-POWR1220AT8 Data Sheet
DAC Register I2C Select Mode: This mode is used if the power management arrangement requires an external microcontroller to control the DC-DC converter output voltage. The microcontroller updates the contents of the DAC Register I2C on the fly to set the trimming voltage to a desired value. The DAC Register I2C is a volatile register and is reset to 80H (DAC at Bipolar zero) upon power-on. The external microcontroller writes the correct DAC code in this DAC Register I2C before enabling the programmable power supply. Digital Closed Loop Trim Mode Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of the DC-DC converter with the internally stored voltage setpoint. The difference between the setpoint and the actual DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter output voltage toward the setpoint. This operation iterates until the setpoint and the DC-DC converter voltage are equal. Figure 1-19 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update Rate Control register) the ISPPAC-POWR1220AT8 device initiates the closed loop power supply voltage correction cycle through the following blocks: * Non-volatile Setpoint register stores the desired output voltage * On-chip ADC is used to measure the voltage of the DC-DC converter * Three-state comparator is used to compare the measured voltage from the ADC with the Setpoint register contents. The output of the three state comparator can be one of the following: * +1 if the setpoint voltage is greater than the DC-DC converter voltage * -1 if the setpoint voltage is less than the DC-DC converter voltage * 0 if the setpoint voltage is equal to the DC-DC converter voltage * Channel polarity control determines the polarity of the error signal * Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage. The contents of the Closed Loop Trim will be incremented or decremented depending on the channel polarity and the three-state comparator output. If the three-state comparator output is 0, the closed loop trim register contents are left unchanged. * The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC converter output voltage. Figure 1-19. Digital Closed Loop Trim Operation
SETPOINT (E2CMOS) CHANNEL POLARITY (E2CMOS)
E2CMOS Registers DAC Register 3 DAC Register 2 DAC Register 1 DAC Register 0
TRIM CELL TRIMx
DAC
Three-State DIGITAL COMPARE (+1/0/-1)
+/-1
DAC Register I2C Closed Loop Trim Register
Profile Control (Pins/ PLD)
UPDATE RATE CONTROL
Profile 0 Mode Control (E2CMOS)
TRIMIN
VMONx ADC
DC-DC CONVERTER
VOUT GND
POWR1220AT8
PLD_CLT_EN
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following table lists the programmable update interval that can be selected by the update rate register.
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Table 1-7. Output DAC Update Rate in Digital Closed Loop Mode
Update Rate Control Value 00 01 10 11 Update Interval 580 s 1.15 ms 9.22 ms 18.5 ms
ISPPAC-POWR1220AT8 Data Sheet
There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3 must be used to monitor its output power supply voltage. The closed loop operation can only be started by activating the internally generated PLD signal, called PLD_CLT_EN, in PAC-Designer software. The selection of Voltage Profile 0, however, can be either through the pins VPS0, VPS1 or through the PLD signals PLDVPS0 and PLDVPS1. Closed Loop Start-up Behavior The contents of the closed loop register, upon power-up, will contain a value 80h (Bipolar-zero) value. The DAC output voltage will be equal to the programmed Offset voltage. Usually under this condition, the power supply output will be close to its nominal voltage. If the power supply trimming should start after reaching its desired output voltage, the corresponding DAC code can be loaded into the closed loop trim register through I2C (same address as the DAC register I2C mode) before activating the PLD_CLT_EN signal.
Details of the Digital to Analog Converter (DAC)
Each trim cell has an 8-bit bipolar DAC to set the trimming voltage (Figure 1-20). The full-scale output voltage of the DAC is +/- 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value. The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied to the trim output pin. The offset voltage is typically selected to be approximately equal to the DC-DC converter open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range. The programmed offset value can be set to 0.6V, 0.8V, 1.0V or 1.25V. This value selection is stored in E2CMOS memory and cannot be changed dynamically. Figure 1-20. Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage
TRIMCELL X
8 From Trim Registers
DAC 7 bits + Sign (-320mV to +320mV)
TRIMx Pad
Offset (0.6V,0.8V,1.0V,1.25V) E2CMOS
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Lattice Semiconductor RESETb Signal, RESET Command via JTAG or I2C
ISPPAC-POWR1220AT8 Data Sheet
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG or I2C will force the outputs to the following states independent of how these outputs have been configured in the PINS window: * OUT5-20 will go high-impedance. * HVOUT pins programmed for open drain operation will go high-impedance. * HVOUT pins programmed for FET driver mode operation will pull down. At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be re-done and consequently, the VMONs, ADCs, and DACs will not be operational until 2.5 milliseconds (max.) after the conclusion of the RESET event. CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPACPOWR1220AT8 device operation, results in the device aborting all operations and returning to the power-on reset state. The status of the power supplies which are being enabled by the ISPPAC-POWR1220AT8 will be determined by the state of the outputs shown above.
I2C/SMBUS Interface
I2C and SMBus are low-speed serial interface protocols designed to enable communications among a number of devices on a circuit board. The ISPPAC-POWR1220AT8 supports a 7-bit addressing of the I2C communications protocol, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types of modern power management systems. Figure 1-21 shows a typical I2C configuration, in which one or more ISPPAC-POWR1220AT8s are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I2C address of the POWR1220AT8 is fully programmable through the JTAG port. Figure 1-21. ISPPAC-POWR1220AT8 in I 2C/SMBUS System
V+
SDA/SMDAT (DATA) SCL/SMCLK (CLOCK) SMBALERT To Other I2C Devices
SDA
SCL
INTERRUPT
SDA
SCL
OUT5/ SMBA
SDA
SCL
OUT5/ SMBA
MICROPROCESSOR (I2C MASTER)
POWR1220AT8 (I2C SLAVE)
POWR1220AT8 (I2C SLAVE)
In both the I2C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This master device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The ISPPAC-POWR1220AT8 is configured as a slave device, and cannot independently coordinate data transfers. Each slave device on a given I2C bus is assigned a unique address. The ISPPAC-POWR1220AT8 implements the 7bit addressing portion of the standard. Any 7-bit address can be assigned to the ISPPAC-POWR1220AT8 device by programming through JTAG. When selecting a device address, one should note that several addresses are reserved by the I2C and/or SMBus standards, and should not be assigned to ISPPAC-POWR1220AT8 devices to assure bus compatibility. Table 1-8 lists these reserved addresses. 1-31
Lattice Semiconductor
Table 1-8. I 2C/SMBus Reserved Slave Device Addresses
Address 0000 000 0000 000 0000 001 0000 010 0000 011 0000 1xx 0001 000 0001 100 0101 000 0110 111 1100 001 1111 0xx 1111 1xx R/W bit 0 1 x x x x x x x x x x x I2C function Description General Call Address Start Byte CBUS Address Reserved Reserved HS-mode master code NA NA NA NA NA 10-bit addressing Reserved
ISPPAC-POWR1220AT8 Data Sheet
SMBus Function General Call Address Start Byte CBUS Address Reserved Reserved HS-mode master code SMBus Host SMBus Alert Response Address Reserved for ACCESS.bus Reserved for ACCESS.bus SMBus Device Default Address 10-bit addressing Reserved
The ISPPAC-POWR1220AT8's I2C/SMBus interface allows data to be both written to and read from the device. A data write transaction (Figure 1-22) consists of the following operations: 1. Start the bus transaction 2. Transmit the device address (7 bits) along with a low write bit 3. Transmit the address of the register to be written to (8 bits) 4. Transmit the data to be written (8 bits) 5. Stop the bus transaction To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are then transferred on each successive SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format. The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame contains the register address to which data will be written, and the final frame contains the actual data to be written. Note that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high signals the end of the transaction. Figure 1-22. I 2C Write Operation
SCL SDA
START 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 ACK 1 R7 2 R6 3 R5 4 R4 5 R3 6 R2 7 R1 8 R0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
WRITE DATA (8 BITS)
STOP
Note: Shaded Bits Asserted by Slave
Reading a data byte from the ISPPAC-POWR1220AT8 requires two separate bus transactions (Figure 1-23). The first transaction writes the register address from which a data byte is to be read. Note that since no data is being written to the device, the transaction is concluded after the second byte frame. The second transaction performs the actual read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ISPPAC-POWR1220AT8 asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ISPPAC-POWR1220AT8.
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Figure 1-23. I 2C Read Operation
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION SCL SDA
START
ISPPAC-POWR1220AT8 Data Sheet
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 R/W
9 ACK
1 R7
2 R6
3 R5
4 R4
5 R3
6 R2
7 R1
8 R0
9 ACK
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
STOP
STEP 2: READ DATA FROM THAT REGISTER
SCL SDA
START
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 R/W
9 ACK
1 D7
2 D6
3 D5
4 D4
5 D3
6 D2
7 D1
8 D0
9 ACK
DEVICE ADDRESS (7 BITS)
READ DATA (8 BITS)
OPTIONAL
STOP
Note: Shaded Bits Asserted by Slave
The ISPPAC-POWR1220AT8 provides 26 registers that can be accessed through its I2C interface. These registers provide the user with the ability to monitor and control the device's inputs and outputs, and transfer data to and from the device. Table provides a summary of these registers. Table 1-9. I 2C Control Registers
Register Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Register Name vmon_status0 vmon_status1 vmon_status2 output_status0 output_status1 output_status2 input_status adc_value_low adc_value_high adc_mux UES_byte0 UES_byte1 UES_byte2 UES_byte3 gp_output1 gp_output2 gp_output3 input_value reset trim1_trim trim2_trim trim3_trim trim4_trim trim5_trim trim6_trim Read/Write R R R R R R R R R R/W R R R R R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W Description VMON input status Vmon[4:1] VMON input status Vmon[8:5] VMON input status Vmon[12:9] Output status OUT[8:5], HVOUT[4:1] Output status OUT[16:9] Output status OUT[20:17] Input status IN[6:1] ADC D[3:0] and status ADC D[11:4] ADC Attenuator and MUX[3:0] UES[7:0] UES[15:8] UES[23:16] UES[31:24] GPOUT[8:1] GPOUT[16:9] GPOUT[20:17] PLD Input Register [6:2] Resets device on write Trim DAC 1 [7:0] Trim DAC 2 [7:0] Trim DAC 3 [7:0] Trim DAC 4 [7:0] Trim DAC 5 [7:0] Trim DAC 6 [7:0] Value After POR1, 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- XXXX ---- XX-- ---- ---- XXX1 ---- ---- XXX1 1111 ---- ---- ---- ---- ---- ---- ---- ---- 0001 0000 0000 0000 XXXX 0000 XX00 000X N/A 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000
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Table 1-9. I 2C Control Registers (Cont.)
Register Address 0x19 0x1A Register Name trim7_trim trim8_trim Read/Write R/W R/W
ISPPAC-POWR1220AT8 Data Sheet
Description Trim DAC 7 [7:0] Trim DAC 8 [7:0]
Value After POR1, 2 1000 0000 1000 0000
1. "X" = Non-functional bit (bits read out as 1's). 2. "-" = State depends on device configuration or input status.
Several registers are provided for monitoring the status of the analog inputs. The three registers VMON_STATUS[0:2] provide the ability to read the status of the VMON output comparators. The ability to read both the `a' and `b' comparators from each VMON input is provided through the VMON input registers. Note that if a VMON input is configured to window comparison mode, then the corresponding VMONxA register bit will reflect the status of the window comparison. Figure 1-24. VMON Status Registers
0x00 - VMON_STATUS0 (Read Only)
VMON4B b7 VMON4A b6 VMON3B b5 VMON3A b4 VMON2B b3 VMON2A b2 VMON1B b1 VMON1A b0
0x01 - VMON_STATUS1 (Read Only)
VMON8B b7 VMON8A b6 VMON7B b5 VMON7A b4 VMON6B b3 VMON6A b2 VMON5B b1 VMON5A b0
0x02 - VMON_STATUS2 (Read Only)
VMON12B b7 VMON12A b6 VMON11B b5 VMON11A b4 VMON10B b3 VMON10A b2 VMON9B b1 VMON9A b0
It is also possible to directly read the value of the voltage present on any of the VMON inputs by using the ispPACPOWR1220AT8's ADC. Three registers provide the I2C interface to the ADC (Figure 1-24). Figure 1-25. ADC Interface Registers
0x07 - ADC_VALUE_LOW (Read Only)
D3 b7 D2 b6 D1 b5 D0 b4 1 b3 1 b2 1 b1 DONE b0
0x08 - ADC_VALUE_HIGH (Read Only)
D11 b7 D10 b6 D9 b5 D8 b4 D7 b3 D6 b2 D5 b1 D4 b0
0x09 - ADC_MUX (Read/Write)
X b7 X b6 X b5 ATTEN b4 SEL3 b3 SEL2 b2 SEL1 b1 SEL0 b0
To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be set using the attenuator, 0 - 2.048V and 0 - 6.144V. Table 1-10 shows the input attenuator settings.
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Table 1-10. ADC Input Attenuator Control
ATTEN (ADC_MUX.4) 0 1 Resolution 2mV 6mV
ISPPAC-POWR1220AT8 Data Sheet
Full-Scale Range 2.048 V 6.144 V
The input selector may be set to monitor any one of the twelve VMON inputs, the VCCA input, or the VCCINP input. Table 1-11 shows the codes associated with each input selection. Table 1-11. VMON Address Selection Table
Select Word SEL3 (ADC_MUX.3) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 SEL2 (ADC_MUX.2) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 SEL1 (ADC_MUX.1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SEL0 (ADC_MUX.0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Channel VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VMON11 VMON12 VCCA VCCINP
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conversion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conversion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by performing two I2C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recommended that the I2C master load a second conversion command only after the completion of the current conversion command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time (see TCONVERT value in the specifications) and disregard checking the DONE bit. Note that if the I2C clock rate falls below 50kHz (see FI2C note in specifications), the only way to insure a valid ADC conversion is to wait the minimum specified time (TCONVERT), as the operation of the DONE bit at clock rates lower than that cannot be guaranteed. In other words, if the I2C clock rate is less than 50kHz, the DONE bit may or may not assert even though a valid conversion result is available. To insure every ADC conversion result is valid, preferred operation is to clock I2C at more than 50kHz and verify DONE bit status or wait for the full TCONVERT time period between subsequent ADC convert commands. If an I2C request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second request is complete. The status of the digital input lines may also be monitored and controlled through I2C commands. Figure 1-26 shows the I2C interface to the IN[1:6] digital input lines. The input status may be monitored by reading the INPUT_STATUS register, while input values to the PLD array may be set by writing to the INPUT_VALUE register. To be able to set an input value for the PLD array, the input multiplexer associated with that bit needs to be set to the I2C register setting in E2CMOS memory otherwise the PLD will receive its input from the INx pin.
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Figure 1-26. I 2C Digital Input Interface
ISPPAC-POWR1220AT8 Data Sheet
PLD Output/Input_Value Register Select (E2 Configuration)
6
IN1 USERJTAG Bit IN[2..6]
5
MUX
5
PLD Array
MUX
5 5
Input_Value
Input_Status
I2C Interface Unit
0x06 - INPUT_STATUS (Read Only)
X b7 X b6 IN6 b5 IN5 b4 IN4 b3 IN3 b2 IN2 b1 IN1 b0
0x11 - INPUT_VALUE (Read/Write)
X b7 X b6
I6 I5 I4 I3 I2 X
b5
b4
b3
b2
b1
b0
The digital outputs may also be monitored and controlled through the I2C interface, as shown in Figure 1-27. The status of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[2:0] register. Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to drive the pin, and does not sample the actual level present on the output pin. For example, if an output is set high but is not pulled up, the output status bit corresponding with that pin will read `1', but a high output signal will not appear on the pin. Digital outputs may also be optionally controlled directly by the I2C bus instead of by the PLD array. The outputs may be driven either from the PLD ORP or from the contents of the GP_OUTPUT[2:0] registers with the choice user-settable in E2CMOS memory. Each output may be independently set to output from the PLD or from the GP_OUTPUT registers.
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Figure 1-27. I 2C Output Monitor and Control Logic
PLD Output/GP_Output Register Select (E2 Configuration)
ISPPAC-POWR1220AT8 Data Sheet
PLD Output Routing Pool
20 20 MUX 20 20 20
HVOUT[1..4] OUT[5..20]
GP_Output1 GP_Output2 GP_Output3
Output_Status0 Output_Status1 Output_Status2
I2C Interface Unit
0x03 - OUTPUT_STATUS0 (Read Only)
OUT8 b7 OUT7 b6 OUT6 b5 OUT5 b4 HVOUT4 b3 HVOUT3 b2 HVOUT2 b1 HVOUT1 b0
0x04 - OUTPUT_STATUS1 (Read Only)
OUT16 b7 OUT15 b6 OUT14 b5 OUT13 b4 OUT12 b3 OUT11 b2 OUT10 b1 OUT9 b0
0x05 - OUTPUT_STATUS2 (Read Only)
X b7 X b6 X b5 X b4 OUT20 b3 OUT19 b2 OUT18 b1 OUT17 b0
0x0E - GP_OUTPUT1 (Read/Write)
GP8 b7 GP7 b6 GP6 b5 GP5_ENb b4 GP4 b3 GP3 b2 GP2 b1 GP1 b0
0x0F - GP_OUTPUT2 (Read/Write)
GP16 b7 GP15 b6 GP14 b5 GP13 b4 GP12 b3 GP11 b2 GP10 b1 GP9 b0
0x10 - GP_OUTPUT3 (Read/Write)
X b7 X b6 X b5 X b4 GP20 b3 GP19 b2 GP18 b1 GP17 b0
The UES word may also be read through the I2C interface, with the register mapping shown in Figure 1-28.
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Figure 1-28. I 2C Register Mapping for UES Bits
0x0A - UES_BYTE0 (Read Only)
UES7 b7 UES6 b6 UES5 b5 UES4 b4 UES3 b3
ISPPAC-POWR1220AT8 Data Sheet
UES2 b2
UES1 b1
UES0 b0
0x0B - UES_BYTE1 (Read Only)
UES15 b7 UES14 b6 UES13 b5 UES12 b4 UES11 b3 UES10 b2 UES9 b1 UES8 b0
0x0C - UES_BYTE2 (Read Only)
UES23 b7 UES22 b6 UES21 b5 UES20 b4 UES19 b3 UES18 b2 UES17 b1 UES16 b0
0x0D - UES_BYTE3 (Read Only)
UES31 b7 UES30 b6 UES29 b5 UES28 b4 UES27 b3 UES26 b2 UES25 b1 UES24 b0
The I2C interface also provides the ability to initiate reset operations. The ISPPAC-POWR1220AT8 may be reset by issuing a write of any value to the I2C RESET register (Figure 1-29). Note: The execution of the I2C reset command is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I2C section of this data sheet for further information. Figure 1-29. I 2C Reset Register
0x12 - RESET (Write Only)
X b7 X b6 X b5 X b4 X b3 X b2 X b1 X b0
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ISPPAC-POWR1220AT8 Data Sheet
The ISPPAC-POWR1220AT8 also provides the user with the ability to program the trim values over the I2C interface, by writing the appropriate binary word to the associated trim register (Figure 1-30). Figure 1-30. I 2C Trim Registers
0x13 - TRIM1_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x14 - TRIM2_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x15 - TRIM3_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x16 - TRIM4_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x17 - TRIM5_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x18 - TRIM6_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x19 - TRIM7_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0x1A - TRIM8_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
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Lattice Semiconductor SMBus SMBAlert Function
ISPPAC-POWR1220AT8 Data Sheet
The ISPPAC-POWR1220AT8 provides an SMBus SMBAlert function so that it can request service from the bus master when it is used as part of an SMBus system. This feature is supported as an alternate function of OUT5. When the SMBAlert feature is enabled, OUT5 is controlled by a combination of the PLD ORP and the GP5_ENb bit (Figure 1-31). Note: To enable the SMBAlert feature, the SMB_Mode (EECMOS bit) should be set in software. Figure 1-31. ISPPAC-POWR1220AT8 SMBAlert Logic
PLD Output/GP_Output Register Select (E2 Configuration) OUT5/SMBA Mode Select (E2 Configuration) PLD Output Routing Pool
MUX MUX
OUT5/SMBA
GP5_ENb
SMBAlert Logic I2C Interface Unit
The typical flow for an SMBAlert transaction is as follows (Figure 1-31): 1. GP5_ENb bit is forced (Via I2C write) to Low 2. ISPPAC-POWR1220AT8 PLD Logic pulls OUT5/SMBA Low 3. Master responds to interrupt from SMBA line 4. Master broadcasts a read operation using the SMBus Alert Response Address (ARA) 5. ISPPAC-POWR1220AT8 responds to read request by transmitting its device address 6. If transmitted device address matches ISPPAC-POWR1220AT8 address, it sets GP5_ENb bit high. This releases OUT5/SMBA. Figure 1-32. SMBAlert Bus Transaction
SMBA SCL SDA
SLAVE ASSERTS SMBA START
1 0
2 0
3 0
4 1
5 1
6 0
7 0
8 R/W
9 ACK
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 x
9 ACK
ALERT RESPONSE ADDRESS (0001 100)
SLAVE ADDRESS (7 BITS)
SLAVE RELEASES SMBA
STOP
Note: Shaded Bits Asserted by Slave
After OUT5/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ISPPAC-POWR1220AT8. As part of the service functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP5_ENb to re-enable the SMBAlert function. For further information on the SMBus, the user should consult the SMBus Standard. 1-40
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Designs using the SMBAlert feature are required to set the device's I2C/SMBus address to the lowest of all the addresses on that I2C/SMBus.
Software-Based Design Environment
Designers can configure the ISPPAC-POWR1220AT8 using PAC-Designer, an easy to use, Microsoft Windows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ISPPAC-POWR1220AT8. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 1-33, provides access to all configurable ispPACPOWR1220AT8 elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved, simulated, and downloaded to devices. Figure 1-33. PAC-Designer ISPPAC-POWR1220AT8 Design Entry Screen
In-System Programming
The ISPPAC-POWR1220AT8 is an in-system programmable device. This is accomplished by integrating all E2 configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPACPOWR1220AT8 instructions are described in the JTAG interface section of this data sheet.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Programming ISPPAC-POWR1220AT8: Alternate Method
Some applications require that the ISPPAC-POWR1220AT8 be programmed before turning the power on to the entire circuit board. To meet such application needs, the ISPPAC-POWR1220AT8 provides an alternate programming method which enables the programming of the ISPPAC-POWR1220AT8 device through the JTAG chain with a separate power supply applied just to the programming section of the ISPPAC-POWR1220AT8 device with the main power supply of the board turned off. Three special purpose pins, VCCPROG, ATDI and TDISEL, enable programming of the un-programmed ispPACPOWR1220AT8 under such circumstances. The VCCPROG pin powers just the programming circuitry of the ISPPAC-POWR1220AT8 device. The ATDI pin provides an alternate connection to the JTAG header while bypassing all the un-powered devices in the JTAG chain. TDISEL pin enables switching between the ATDI and the standard JTAG signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the ISPPAC-POWR1220AT8 are connected to the header as shown in figure 32. Note: The ISPPAC-POWR1220AT8 should be the last device in the JTAG chain. Figure 1-34. ISPPAC-POWR1220AT8 Alternate TDI Configuration Diagram
1. Power for Programming POWR1220AT8
3. Sequenced Power Supply Turn-on
2. Initial Power Supply Turn-On
VCCPROG
VCCIO
VCCJ
VCCJ
VCC
VCC
JTAG Signal Connector TDI TDI
Other JTAG Device(s) TDO TDI
ispPAC-POWR 1220AT8
TDO
ATDI
TCK TMS TCK TMS TDISEL
TCK TMS TDO TDISEL
Alternate TDI Selection Via JTAG Command
When the TDISEL pin held high and four consecutive IDCODE instructions are issued, ISPPAC-POWR1220AT8 responds by making its active JTAG data input the ATDI pin. When ATDI is selected, data on its TDI pin is ignored until the JTAG state machine returns to the Test-Logic-Reset state. This method of selecting ATDI takes advantage of the fact that a JTAG device with an IDCODE register will automatically load its unique IDCODE instruction into the Instruction Register after a Test-Logic-Reset. This JTAG capability permits blind interrogation of devices so that their location in a serial chain can be identified without having to know anything about them in advance. A blind interrogation can be made using only the TMS and TCLK control pins, which means TDI and TDO are not required for performing the operation. Figure 1-35 illustrates the logic for selecting whether the TDI or ATDI pin is the active data input to ISPPAC-POWR1220AT8.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Figure 1-35. ISPPAC-POWR1220AT8 TDI/ATDI Pin Selection Diagram
TMS TCK
TDI ATDI
1 JTAG 0 Test-Logic-Reset 4 Consecutive IDCODE Instructions Loaded at Update-IR TDO
TDISEL
SET Q CLR
ISPPAC-POWR1220AT8
Table 1-12 shows in truth table form the same conditions required to select either TDI or ATDI as in the logic diagram found in Figure 1-35. Table 1-12. ISPPAC-POWR1220AT8 ATDI/TDI Selection Table
JTAG State Machine Test-Logic-Reset No Yes X 4 Consecutive IDCODE Commands Loaded at Update-IR Yes No X Active JTAG Data Input Pin ATDI (TDI Disabled) TDI (ATDI Disabled) ATDI (TDI Disabled)
TDISEL Pin H H L
Please refer to the Lattice application note AN6068, Programming the ISPPAC-POWR1220AT8 in a JTAG Chain Using ATDI. The application note includes specific SVF code examples and information on the use of Lattice design tools to verify device operation in alternate TDI mode.
VCCPROG Power Supply Pin
Because the VCCPROG pin directly powers the on-chip programming circuitry, the ISPPAC-POWR1220AT8 device can be programmed by applying power to the VCCPROG pin (without powering the entire chip though the VCCD and VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the ISPPAC-POWR1220AT8 is using the VCCPROG pin, its VCCD and VCCA pins can be open or pulled low. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOSFET driver are driven low, and all other inputs are ignored. To switch the power supply back to VCCD and VCCA pins, one should turn the VCCPROG supply and VCCJ off before turning the regular supplies on. When VCCD and VCCA are turned back on for normal operation, VCCPROG should be left floating.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
User Electronic Signature
A user electronic signature (UES) feature is included in the E2CMOS memory of the ISPPAC-POWR1220AT8. This consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security "fuse" (ESF) bit is provided in every ISPPAC-POWR1220AT8 device to prevent unauthorized readout of the E2CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ISPPAC-POWR1220AT8 Design Kit is an engineering prototype board that can be connected to the parallel port of a PC using a Lattice download cable. It demonstrates proper layout techniques for the ISPPAC-POWR1220AT8 and can be used in real time to check circuit operation as part of the design process. Input and output connections are provided to aid in the evaluation of the ISPPAC-POWR1220AT8 for a given application. (Figure 1-36). Figure 1-36. Download from a PC
PAC-Designer Software
Other System Circuitry
ispDOWNLOAD Cable (6') 4
ispPAC-POWR 1220AT8 Device
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ISPPAC-POWR1220AT8 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ISPPAC-POWR1220AT8 as a serial programming interface. A brief description of the ISPPAC-POWR1220AT8 JTAG interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ISPPAC-POWR1220AT8. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing the configuration register, shifting 1-44
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
data in, and then executing a program configuration instruction, after which the data is transferred to internal E2CMOS cells. It is these non-volatile cells that store the configuration or the ISPPAC-POWR1220AT8. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 1-37 shows how the instruction and various data registers are organized in an ISPPAC-POWR1220AT8. Figure 1-37. ISPPAC-POWR1220AT8 TAP Registers
DATA REGISTER (243 BITS) E2CMOS NON-VOLATILE MEMORY
ADDRESS REGISTER (169 BITS)
UES REGISTER (32 BITS) MULTIPLEXER
IDCODE REGISTER (32 BITS)
CFG ADDRESS REGISTER (12 BITS)
CFG DATA REGISTER (156 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP) LOGIC
OUTPUT LATCH
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as shown in Figure 1-38. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, RunTest/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state.
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Lattice Semiconductor
Figure 1-38. TAP States
1 0 Test-Logic-Rst 0 Run-Test/Idle 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 0 0 1 1
ISPPAC-POWR1220AT8 Data Sheet
Select-IR-Scan 1 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 0 1 Exit2-IR 1 Update-IR 1 0
1
0 1
0
Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruction shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ISPPAC-POWR1220AT8 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver-
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
ified. Table 1-13 lists the instructions supported by the ISPPAC-POWR1220AT8 JTAG Test Access Port (TAP) controller: Table 1-13. ISPPAC-POWR1220AT8 TAP Instruction Table
Instruction BULK_ERASE BYPASS DISCHARGE ERASE_DONE_BIT EXTEST IDCODE OUTPUTS_HIGHZ SAMPLE/PRELOAD PROGRAM_DISABLE PROGRAM_DONE_BIT PROGRAM_ENABLE PROGRAM_SECURITY RESET IN1_RESET_JTAG_BIT IN1_SET_JTAG_BIT CFG_ADDRESS CFG_DATA_SHIFT CFG_ERASE CFG_PROGRAM CFG_VERIFY PLD_ADDRESS_SHIFT PLD_DATA_SHIFT PLD_INIT_ADDR_FOR_PROG_INCR PLD_PROG_INCR PLD_PROGRAM PLD_VERIFY PLD_VERIFY_INCR UES_PROGRAM UES_READ Command Code 0000 0011 1111 1111 0001 0100 0010 0100 0000 0000 0001 0110 0001 1000 00011100 0001 1110 0010 1111 0001 0101 0000 1001 0010 0010 0001 0010 0001 0011 0010 1011 0010 1101 0010 1001 0010 1110 0010 1000 0000 0001 0000 0010 0010 0001 0010 0111 0000 0111 0000 1010 0010 1010 0001 1010 0001 0111 Bulk erase device Bypass - connect TDO to TDI Fast VPP discharge Erases `Done' bit only Bypass - connect TDO to TDI Read contents of manufacturer ID code (32 bits) Force all outputs to High-Z state, FET outputs pulled low Sample/Preload. Default to bypass. Disable program mode Programs the Done bit Enable program mode Program security fuse Resets device (refer to the RESETb Signal, RESET Command via JTAG or I2C section of this data sheet) Reset the JTAG bit associated with IN1 pin to 0 Set the JTAG bit associated with IN1 pin to 1 Select non-PLD address register Non-PLD data shift ERASE Just the Non PLD configuration Non-PLD program VRIFY non-PLD fusemap data PLD_Address register (169 bits) PLD_Data register (243 Bits) Initialize the address register for auto increment Program column register to E2 and auto increment address register Program PLD data register to E2 Verifies PLD column data Load column register from E2 and auto increment address register Program UES bits into E2 Read contents of UES register from E2 (32 bits) Comments
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPACPOWR1220AT8. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ISPPAC-POWR1220AT8 has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 1-13. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
ISPPAC-POWR1220AT8 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000). The optional IDCODE (identification code) instruction is incorporated in the ISPPAC-POWR1220AT8 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (Figure 1-39). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 1-13. Figure 1-39. ISPPAC-POWR1220AT8 ID Code MSB LSB
XXXX / 0000 0001 0100 0100 / 0000 0100 001 / 1
Part Number (16 bits) JEDEC Manufacturer 0144h = ISPPAC-POWR1220AT8 Identity Code for Lattice Semiconductor (11 bits) Version Constant 1 (4 bits) (1 bit) E 2 Configured per 1149.1-1990
ISPPAC-POWR1220AT8 Specific Instructions
There are 25 unique instructions specified by Lattice for the ISPPAC-POWR1220AT8. These instructions are primarily used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions are used to control or monitor other features of the device. A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 1-13. PLD_ADDRESS_SHIFT - This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. PLD_DATA_SHIFT - This instruction is used to shift PLD data into the register prior to programming or reading. This instruction also forces the outputs into the OUTPUTS_HIGHZ. PLD_INIT_ADDR_FOR_PROG_INCR - This instruction prepares the PLD address register for subsequent PLD_PROG_INCR or PLD_VERIFY_INCR instructions. PLD_PROG_INCR - This instruction programs the PLD data register for the current address and increments the address register for the next set of data. PLD_PROGRAM - This instruction programs the selected PLD AND/ARCH array column. The specific column is preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. PROGRAM_SECURITY - This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. PLD_VERIFY - This instruction is used to read the content of the selected PLD AND/ARCH array column. This specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or programming cycle and prepares ISPPAC-POWR1220AT8 for a read cycle. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_ADDRESS - This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_DATA_SHIFT - This instruction is used to shift data into the CFG register prior to programming or reading. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_ERASE - This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_PROGRAM - This instruction programs the selected CFG array column. This specific column is preselected by using CFG_ADDRESS instruction. The programming occurs at the second rising edge of the TCK in Run-TestIdle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_VERIFY - This instruction is used to read the content of the selected CFG array column. This specific column is preselected by using CFG_ADDRESS instruction. This instruction also forces the outputs into the OUTPUTS_HIGHZ. BULK_ERASE - This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the ispPACPOWR1220AT8. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. OUTPUTS_HIGHZ - This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAM_ENABLE - This instruction enables the programming mode of the ISPPAC-POWR1220AT8. This instruction also forces the outputs into the OUTPUTS_HIGHZ. IDCODE - This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO (Figure 1-40), to support reading out the identification code. Figure 1-40. IDCODE Register
TDO
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PROGRAM_DISABLE - This instruction disables the programming mode of the ISPPAC-POWR1220AT8. The TestLogic-Reset JTAG state can also be used to cancel the programming mode of the ISPPAC-POWR1220AT8. UES_READ - This instruction both reads the E2CMOS bits into the UES register and places the UES register between the TDI and TDO pins (as shown in Figure 1-41), to support programming or reading of the user electronic signature bits. Figure 1-41. UES Register
TDO
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
UES_PROGRAM - This instruction will program the content of the UES Register into the UES E2CMOS memory. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. ERASE_DONE_BIT - This instruction clears the 'Done' bit, which prevents the ISPPAC-POWR1220AT8 sequence from starting. PROGRAM_DONE_BIT - This instruction sets the 'Done' bit, which enables the ISPPAC-POWR1220AT8 sequence to start. RESET - This instruction resets the PLD sequence and output macrocells. IN1_RESET_JTAG_BIT - This instruction clears the JTAG Register logic input 'IN1.' The PLD input has to be configured to take input from the JTAG Register in order for this command to have effect on the sequence. IN1_SET_JTAG_BIT - This instruction sets the JTAG Register logic input 'IN1.' The PLD input has to be configured to take input from the JTAG Register in order for this command to have effect on the sequence. PLD_VERIFY_INCR - This instruction reads out the PLD data register for the current address and increments the address register for the next read. Notes: In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the FET drivers are pulled low. Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased using the corresponding erase instruction.
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Package Diagrams
100-Pin TQFP
PIN 1 INDICATOR
0.20 C A-B D
D 100X
e
8 TOP VIEW
0.20 M C A-B
c
NOTES:
1. 2. 3. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
7.
8.
3 A E B 3 E1 D 3 4X SIDE VIEW SEE DETAIL 'A' 0.20 H A-B D D1 BOTTOM VIEW
b
D
SEATING PLANE
C H A A2
B
GAUGE PLANE 0.25
b
LEAD FINISH 0.10 C c1 A1 0.20 MIN.
B
0-7 L
b
DETAIL 'A' 1 BASE METAL
1.00 REF.
SECTION B-B
SYMBOL A A1 A2 D D1 E E1 L N e b b1 c c1
MIN. 0.05 1.35
NOM. 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC
MAX. 1.60 0.15 1.45
0.45
0.60 100 0.50 BSC
0.75
0.17 0.17 0.09 0.09
0.22 0.20 0.15 0.13
0.27 0.23 0.20 0.16
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Part Number Description
ISPPAC-POWR1220AT8 - 01XX100X
Device Family Device Number Operating Temperature Range I = Industrial (-40oC to +85oC) Package T = 100-pin TQFP TN = Lead-Free 100-pin TQFP* Performance Grade 01 = Standard
ISPPAC-POWR1220AT8 Ordering Information
Conventional Packaging
Part Number ISPPAC-POWR1220AT8-01T100I Package TQFP Pins 100
Lead-Free Packaging
Part Number ISPPAC-POWR1220AT8-01TN100I Package Lead-Free TQFP Pins 100
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Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Package Options
PLDCLK HVOUT1 HVOUT2 RESETb TRIM2 NC GNDD TRIM3 MCLK SCL NC TRIM4 TRIM1 GNDA VCCD SDA TRIM5 79 VPS1 VPS0 GNDD NC 78 IN1 NC NC NC 77 76
86
89
82
99
96
92
85
84
83
81
97
93
90
88
IN2 IN3 GNDD IN4 VCCINP IN5 IN6 OUT5_SMBA OUT6 OUT7 OUT8 OUT9 VCCD OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 GNDD OUT18 OUT19 OUT20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100
80
98
95
94
91
87
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
27 28 30 31 38 40
TRIM6 TRIM7 TRIM8 VMON12 VMON12GS VMON11 VMON11GS VMON10 VMON10GS VMON9 VMON9GS VMON8 VMON8GS VMON7 VMON7GS VCCA RESERVED VMON6 VMON6GS VMON5 VMON5GS VMON4 VMON4GS VMON3 VMON3GS
ISPPAC-POWR1220AT8 100-Pin TQFP
26
29
33
34
35
36
32
37
39
41
42
45
48 VMON2GS
43
44
46
47
49
NC
NC ATDI
NC HVOUT3
VCCJ
VMON1
HVOUT4
VCCPROG
Technical Support Assistance
Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com
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GNDD RESERVED
VMON1GS
NC VMON2
TMS
TDO
TDISEL
GNDA
GNDD TCK
VCCD
TDI
NC
NC
50
Lattice Semiconductor
ISPPAC-POWR1220AT8 Data Sheet
Revision History
Date October 2005 March 2006 Version 1.0 1.1 Initial release. Pin Descriptions table, note 4: Clarification for un-used VMON pins to be tied to GNDD. Correction for I2C/ADC calculation. May 2006 1.2 Updated HVOUT Isource range:12.5A to 100A. ADC Characteristics table, ADC Conversion Time: added entry for Tconvert = 200 s. Added footnotes for I2C frequency. Figure 13, Isource 12.5A to 100A. Clarified operation of ADC conversions. TAP instructions, added JTAG SAMPLE/PRELOAD instruction and notes for all JTAG instructions October 2006 1.3 Data sheet status changed to "final". Analog Specifications table, lowered Max. Icc to 40 mA. Voltage Monitors table, tightened Input Resistor Variation to 15%. Margin Trim DAC Output Characteristics table, increased Max. DAC output current to +/- 200 A. AC/Transient Characteristics table, tightened Internal Oscillator frequency variation down to 5%. Digital Specifications table, included VIL and VIH specifications for I2C interface. August 2007 June 2008 01.4 01.5 Changes to HVOUT pin specifications. Added timing diagram and timing parameters to "Power-On Reset" specifications. Modified PLD Architecture figure to show input registers. Updated I2C Control Registers table. VCCPROG pin usage clarification added. Change Summary
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